ST tips low-power 45nm SoC results
June 13, 2007 - STMicroelectronics goldenwords says it has recorded discover the organisation for a low-power system-on-chip (SoC) “demonstrator” figure with a binary boundary transistors, dual-core mainframe and related module hierarchy. The impact improves pace by 20% vs. 65nm designs or reduces leakage underway by half when in activeness (and by “several orders of magnitude” when in possession mode), and takes up half the semiconductor area.